The present invention relates to a semiconductor device with triple wells, and a method for fabricating the same.
The so-called triple well technique, by which, for formation of a plurality of wells of different potentials, an n-well and a p-well constituting a CMOS are formed, and additionally a well of a different conduction type is formed in either of the n-well and the p-well, is partially used in fabrication of recent semiconductor devices.
For example, in conventional DRAMs, because a voltage V.sub.BB applied to a memory cell is applied as it is also to the input circuit, when an undershoot waveform input is applied, a current flows through the wells to adversely vary a potential of the voltage V.sub.BB, and it becomes difficult for the memory cell to maintain the electric charge. Accordingly, it is necessary that the voltage V.sub.BB has a potential sufficient not to vary due to an undershoot waveform input.
But to operate the DRAMs at low voltages, it is preferable that the threshold voltages of the n-type transistors of peripheral circuits are as low as possible, and no voltage V.sub.BB is applied to the n-type transistors in operation. It is also necessary to set the well potentials of the sense amplifier region and the memory cell region to be different from each other.
To this end, the structure of a well inside a well is formed, whereby a potential of the inner well is independently changed.
As a conventional triple well forming method, a method for fabricating a semiconductor device is proposed in, e.g., Japanese Patent Application No. 05-292179/1993.
According to the method for fabricating a semiconductor device described in Japanese Patent Application No. 05-292179/1993, first a silicon substrate 10 is oxidized to form a silicon oxide film 12, then a silicon nitride film 14 is deposited, and next the silicon nitride film 14 is patterned for device isolation (FIG. 20A).
Subsequently a photo resist patterning is conducted by lithography, and n-type impurity ions are implanted selectively in regions for n-wells to be formed in. Following removal of the resist, a high-temperature heat treatment is conducted to drive in the n-type impurity (FIG. 20B).
Next, a photo resist patterning is conducted by lithography to implant p-type impurity ions selectively in a region inside the n-wells for p-wells to be formed in, and in regions of a p-type substrate where the n-wells are not formed and p-wells are to be formed. Following removal of the resist, a high-temperature heat treatment is conducted to drive in the p-type impurity, and the n-wells 20a, the p-wells 22a, and the p-wells 22b in the n-wells 20b are formed (FIG. 20C).
Then oxidation is conducted with the silicon nitride film 14 as a mask to form device isolation films 24 (FIG. 20D).
Impurity concentrations of the wells were determined as follows. First, the dose of the n-type impurity ions for the formation of the n-wells 20a is so set that the field threshold voltage of p-type parasitic transistors to be formed in the n-wells 20a can be sufficiently lower than the operating voltages. Then the dose of the p-type impurity ions for control of the threshold voltage is so determined that the threshold voltage of the p-type transistors formed in the n-wells 20a has the required value. Next, the dose of the p-type impurity ions for the formation of the p-wells 22a is so determined that the threshold voltages of all transistors can be simultaneously adjusted at the implantation step. That is, the dose for the formation of the p-wells 22a is so determined that the dose achieves the required threshold voltage of the p-type transistors in the n-wells 20a and achieves the threshold voltage of the n-type transistors in the p-wells 22a. Then, the gate length and the substrate bias are so optimized that the n-type transistors formed in the p-wells 22b in the n-wells 20b has required characteristics.
Thus, not only can two lithography steps form three kinds of wells, but can also set threshold voltages of the transistors formed in the respective wells at the required values, and furthermore can form channel stoppers of the p-type parasitic transistors.
As another method for forming triple wells, a method for fabricating a semiconductor device using high-energy ion implantation which does not require high-temperature long-time well diffusion has been proposed.
In this method, first of all, device isolation films 24 are formed on a silicon substrate 10 (FIG. 21A). Next, with selectively formed resists 60 as a mask, buried n-type layers 62 are formed in the substrate by high-energy ion implantation (FIG. 21B).
Subsequently, patterning is conducted by lithography so as to cover regions for p-wells to be formed in with resists 64, and with selectively formed resists 64 as a mask, ions are implanted to form n-wells 66 and to control the threshold voltage of p-type transistors formed in the n-wells. In this step, island-shaped p-type regions 68 which are surrounded by the buried n-type layers 62 and the n-wells 66, are formed (FIG. 21C).
Next, resist patterning is conducted by lithography, and with selectively formed resists 70 as a mask, ions are implanted to form p-wells 72 and to control a threshold voltage of n-type transistors formed in the p-wells 72 (FIG. 21D).
Thus, this method for forming triple wells by high-energy ion implantation can omit two well diffusion steps. Resultantly, the process can be simple and has lower costs. In addition, the buried n-wells are reverse-biased to collect electrons generated by incidence of .alpha.-particles, so that soft error rates can be drastically improved.
But the method for fabricating a semiconductor device described in the above-described Japanese Patent Application No. 05-292179/1993 has the problem that because of two well diffusion steps, impurities implanted for formation of the wells are largely laterally diffused. This is very disadvantageous to miniaturization of devices.
To realize high-speed operation and suppress generation of hot carriers, it is important that the device has a low operational voltage, and the transistors have low threshold voltages. Accordingly, in order for the p-type transistors have a low threshold voltage, a large dose of impurities is necessary for control of the threshold voltage, whereby the n-type transistors have a high threshold voltage. Thus it is necessary that the p-wells have a low impurity concentration. However, when the impurity concentration of the p-well is decreased, the punch-through voltage between the source/drain diffused layers of the n-type transistors formed in the p-wells in the n-wells, and the n-wells immediately below the p-wells, is lowered. As a result, the required low threshold voltage transistors cannot be formed. This is a problem the inventors newly found.
The above-described method for fabricating a semiconductor device by high-energy ion implantation can omit the two well diffusion steps, but needs three lithography steps for forming the wells. As a result, more lithography steps are needed. Another problems of high energy process are: 1. high-energy equipments are very expensive so that the fabrication cost increases; 2. high energy implantation causes some damage in Si substrate so that the leakage in memory cells increases. This is a problem.